This application claims priority under 35 USC § 119 to Korean Patent Application No. 2006-51408, filed on Jun. 8, 2006 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to fabrication of integrated circuits, and more particularly to fabricating structures of different types of field effect transistors with high integrity.
2. Description of the Related Art
Integrated circuits such as semiconductor memory devices generally include transistors such as MOSFETs (metal oxide semiconductor field effect transistors). MOSFETs having various structures and characteristics may be used in a semiconductor memory device. For example, a MOSFET of a planar type or a MOSFET with one fin is formed in a cell area of a semiconductor memory device. Additionally for improved response speed with increased channel regions, a MOSFET with multiple fins is formed in a peripheral area and a core area of the semiconductor memory device. Furthermore, another MOSFET of the planar type is formed in the peripheral area and the core area.
Processes for fabricating such transistors with different structures and characteristics may be complicated, and such transistors may have failures generated from such fabrication processes. For example, a MOSFET of a planar type and a MOSFET with multiple fins are simultaneously formed on different areas of a semiconductor substrate. In that case, a first gate oxide layer and a first gate conductive layer for the MOSFET of the planar type are formed in first and second active regions of the substrate. Portions of the first gate oxide layer and the first gate conductive layer in the second active region are removed to expose the second active region of the substrate.
Thereafter, a second gate oxide layer and a second gate conductive layer are formed on the multiple fins exposed in the second active region of the substrate. During removal of the first gate oxide layer from the second active region, the fins in the second active region may be etched to be degraded structurally. For example, the widths of the fins may be excessively reduced. Alternatively, during formation of the first gate oxide, the fins in the second active region may be oxidized. Such changes to the fins would deteriorate characteristics of the MOSFETs formed in the second active region.
Further, thermal budgets may be created for the first gate conductive layer and the first gate oxide layer during several oxidation processes performed at high temperature for the structures subsequently formed in the second active region. Additionally when the second gate conductive layer is formed with metal, the first gate conductive layer may be contaminated during formation of the second gate conductive layer. Such contamination may cause failure in the MOSFET of the planar type in the first active region.
Thus, a mechanism for fabricating field effect transistors of different types with high performance integrity is desired.